The present invention relates to a technology of exclusively controlling a shared resource under plural OS's (Operating Systems) running on a multi-core processor (multiprocessor). More particularly, the invention relates to a multiprocessor that exclusively controls a shared resource without using inter-OS lock.
Recently, there is an increasing demand to improve the processor performance in various fields such as multimedia processing and high-definition image processing. However, present LSI (Large Scale Integrated circuit) technologies have limitations in device acceleration. As a solution, parallel processing is receiving increasing attention. Multiprocessor systems are aggressively researched and developed.
Generally, the inter-OS lock provides exclusive control over access to a resource shared by the OS's that are running on a multi-core processor (multiprocessor). The related technologies include the inventions disclosed in patent documents 1 through 3 and the technology disclosed in non-patent document 1 as shown below.
Patent document 1 aims to provide a processor system integrating plural CPUs with a semiconductor device capable of less overhead and improved power saving. The multi-core processor includes the clock stop feature, the clock restart feature, and the interrupt control circuit. The clock stop feature enables a package to perform one or more OS's and application programs and, while they are performed, changes one or more CPUs to an energy saving state that consumes less power than CPU operations. The clock restart feature is available within a chip and releases the energy saving state enabled by the clock stop feature for one or more CPUs. The interrupt control circuit is available between chips in the package and releases the energy saving state enabled by the clock stop feature for one or more CPUs.
Patent document 2 aims to provide a multiprocessor system capable of greatly reducing power consumption. Processor A controls a clock frequency control portion to change the frequency of a clock input to processor A in accordance with a ratio between estimated process time Ta for program A and estimated process time Tb for program B. Processor A also controls a variable power supply to change a power supply voltage supplied to processor A in accordance with the frequency of a clock input to processor A. Accordingly, it is possible to greatly decrease power consumption for processor A.
Patent document 3 discloses the method and the apparatus for changing multi-core processor configurations. According to one embodiment, the throttle module (or throttle logic) can find the quantity of parallelism in a currently executed program and change thread execution of the program in various cores. If the quantity of parallelism is large, the processor can be configured to execute a large amount of thread in a core configured to consume less power. If the quantity of parallelism is small, the processor can be configured to execute a small amount of thread in a core configured to provide better scalar performance.
Non-patent document 1 discloses the exclusive control of access to shared memory as a resource shared among OS's using a synchronous instruction of the processor.    Patent Document 1: Japanese Unexamined Patent Publication No. 2010-140319    Patent Document 2: Japanese Unexamined Patent Publication No. 2002-215599    Patent Document 3: Japanese Translation of Unexamined PCT Application No. 2008-513912    Non-Patent Document 1: Sugai, Endou, Yamaguchi, and Kondou. Implementation of hybrid OS environment on a single-chip multiprocessor—Implementation of an inter-OS interface—Information Processing Society of Japan, National convention 2D-6, March 2004.